Main Content
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Used Verilog and MATLAB to develop RTL of a non-linear correction engine, with functional pipelining interleaved channels; applied piecewise Horner’s iterative polynomial fitting algorithm to ease the computational burden
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Programed testbench to verify the non-linear correction system
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Synthesized post-layout timing and power of the system with IC Compiler, and optimized the energy per ADC sample while guarantee the ENOB
Correction Algorithm
An analog-to-digital converter (ADC) will act as the front end of the low-power design, and in the design we need the ADC with 15-bit resolution.
By sweeping the voltage input to the ADC we get the output voltage sweep and realize that the reason for the significant degradation of bit resolution is the implementation-inherent nonlinearity of the ADC. Assuming the design of the ADC is finalized and can’t be changed, we have to recover bits in the digital domain. Instead of redesigning the ADC we can take an easy approach and correct the non-linear mapping such to reach your target ENOB as below.
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1. Four Section Piecewide Fitting Algorithm
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2. Horner's Iterative Polynomial Fitting Algorithm
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Design Blocks and Codes - Verilog
Total codes more than 10000 lines
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Testbench - Verilog
Use Verilog to write testbench for both non-interleaving 16 channel and interleaving 16 channel
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Efficiency - IC Compiler
Use IC Compiler for calculation of power and core area.
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Course Project of Design of VLSI Circuits and Systems
ADC Non-Linear Correction
1. 16 channel non-interleaving codes (Finite-state-machine)
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2. 16 channel interleaving codes (Clock)
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